At 2D Photonics and CamGraPhIC we develop ultra-high bandwidth, low latency optical interconnects for generative AI, cellular, and high bandwidth data transfer applications. The way we incorporate graphene with silicon photonics preserves its unique electrooptical properties and enables a next generation of optical interconnect devices with reduced electronic complexity, improved energy consumption, and higher channel density. At CamGraPhIC in Pisa, Italy we run the 700 sqm Inphotec Graphene Photonics development facility, where our team of industry-leading scientists, process development and photonics engineers are pioneering the design and fabrication of Photonic Integrated Circuits (PICs) incorporating Graphene. We are seeking a Lead IC Layout Engineer to establish and lead the layout function for advanced Electronic Integrated Circuits (EICs). This role is ideal for a hands-on technical leader who can build and mentor a layout team while personally owning critical analog, digital, and mixed-signal layout at 7 nm and Own hands-on layout of critical analog, digital, and mixed-signal blocks in advanced FinFET Defne and maintain layout methodologies, best practices, and quality standards • Manage the CAD and PDK environment, including tool setup, version control, and foundry Prepare fnal databases and documentation for foundry mask release and tape-out Strong experience with both analog and digital layout, including mixed-signal integration • Track record of successful tape-outs and foundry mask releases •