Role Overview As an MCU SOC Architect, you will define and drive the architecture of next‑generation microcontrollers. You will lead architectural decisions that balance real‑time determinism, performance, power efficiency, safety and security, enabling scalable MCU products across industrial, automotive and IoT markets. You will work closely with SOC design teams, system architects, IP owners, software architects and product planning to deliver competitive, production‑ready architectures. This role requires deep expertise across MCU architectures, SOC integration, clock/reset/power design, memory subsystems and microarchitectural trade‑offs, with a strong focus on real‑time and low‑power constraints. Key Responsibilities Lead the definition and evolution of MCU SOC architectures aligned with product strategy, market trends and industry standards. Design scalable and efficient multi‑core compute architectures, optimizing for TCMs, SRAM hierarchy, DMA and interconnect bandwidth. Define and integrate secure boot, root‑of‑trust, isolation and cryptographic acceleration; ensure architectures support functional safety and lifecycle requirements. Collaborate with hardware, firmware and IP teams to enable seamless integration of processing, memory, power management, peripherals and interconnect subsystems; a good understanding of Analog IPs (ADC, DAC, PLL, SERDES, etc.) will be required. Lead architectural strategies to optimize performance per watt, balancing frequency, voltage, memory and power states to meet real‑time and low‑power envelopes; support early performance and power estimation to reduce product risk. Develop architecture specifications, best practices and technical documentation to guide development teams. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or a related field. Proven experience in MCU SOC architecture, microarchitecture, RTL design and/or physical design. Strong understanding of microprocessor and microcontroller architectures, including CPU cores, interconnects, memory management, bus protocols and peripheral integration. Experience in low‑power design and performance optimization. Familiarity with Ethernet, USB, SPI and I3C protocols. Strong collaboration skills across silicon, hardware and software teams. Preferred Qualifications Experience with ARM Cortex‑M architectures. Background in power and performance modeling, HW/SW co‑design and debugging. Knowledge of functional safety and security standards. Familiarity with Wi‑Fi integration, networking protocols and secure wireless communication. #J-18808-Ljbffr